1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly relates to a semiconductor memory device including memory cells, which have specific or distinctive structures, as well as a semiconductor memory device having a memory cell array, which has a specific or distinctive structure.
2. Description of the Background Art
A memory cell of one-transistor and one-capacitor structure is liable to loose its information, and particularly, data at a high potential level (H-data) due to leak of electric charges stored in the capacitor. In recent years, such a method has been proposed that uses two memory cells for writing H-data and L-data (i.e., data at a lower potential than H-data) therein, respectively. This method is devised to utilize a difference in amount of stored electric charges between the two memory cells, and thereby provide a Dynamic Random Access Memory (DRAM) performing a larger operation.
However, the above method requires two transistors and two capacitors, and therefore suffers from such a problem that areas of the memory cells are large. Accordingly, it has been desired to develop a semiconductor memory device, which does not occupy a large area, and can hold data with high stability.
An object of the invention is to provide a semiconductor memory device using memory cells, which have structures not increasing areas, and are arranged in a distinctive manner providing high data holding stability.
According to a first aspect of the invention, a semiconductor memory device includes memory cells formed on a main surface of a semiconductor substrate and each having first and second transistors each having a gate electrode and impurity regions forming source/drain as well as one capacitor, and bit and word lines for controlling an operation of the memory cells. In this semiconductor memory device, a cell plate of the capacitor is formed of the same layer as the gate electrode.
According to this structure, the memory cell can have the structure including the two transistors, which are arranged on the cell plate side and the storage node side with the one capacitor therebetween, respectively. Therefore, the memory cell having high signal holding stability can be formed by devising control. Since the memory cell employs only one capacitor, the memory cell occupies only a small area.
According to the structure described above, the cell plate and the gate electrode can be formed of the same interconnection layers. Therefore, formation of the memory cell structure including the memory cell capacitor and formation of the transistors can be performed in parallel with each other within the same manufacturing steps, and therefore, the manufacturing steps can be simplified. The xe2x80x9csame interconnection layersxe2x80x9d described above mean the interconnection layers arranged at the same level, having the same thickness and made of the same material. The semiconductor memory device according to the invention may be a DRAM, an ERAM and others. This is true also with respect to semiconductor memory devices, which will be described later.
In the semiconductor memory device of the first aspect, the cell plate may be in electrical communication with the impurity region of the first transistor, and may be opposed to the impurity region of the second transistor with a dielectric layer therebetween.
Owing to the above structure, the memory cell can have the capacitor arranged between the two transistors. The impurity regions described above may include an impurity region, which is enlarged and deformed as compared with an impurity region of a normal transistor for increasing the capacitance of the capacitor.
The semiconductor memory device of the first aspect may have an interconnection layer located at the same level as the bit line. The interconnection layer may have a side connected to the impurity region of the first transistor via a first plug interconnection as well as another side connected to the cell plate via a second plug interconnection.
According to this structure, an interconnection for connection between the cell plate and the first transistor can be arranged within a space between the bit lines. As a result, the interconnection layer can be simple.
The semiconductor memory device of the first aspect may include a plug interconnection overlapping, in a plan view, with a side edge of the cell plate and a side edge of the impurity region of the first transistor. A portion of the plug interconnection overlapping with the side edge of the cell plate may be in contact with the cell plate, and a portion of the plug interconnection overlapping with the impurity region of the first transistor may be in contact with the impurity region of the first transistor.
Owing to the above structure, only one plug interconnection is required for establishing the foregoing connection. Therefore, the connection between the impurity region of the first transistor and the cell plate can be achieved by an extremely simple structure. The bit line is merely required to avoid the upper end of the plug interconnection. This increases the flexibility in planar arrangement of the bit line. For example, all the bit lines can be arranged linearly. Therefore, the layout of the bit line can be simple.
The semiconductor memory device according to the first aspect may include an insulating layer at a level lower than the impurity regions of the first and second transistors for interrupting conduction between the impurity regions and its lower side.
This structure can effectively prevent leak of electric charges from the memory capacitor. The insulating layer may be formed by implanting oxygen ions. Alternatively, a substrate such as an SOI (Substrate on Insulator) provided with an insulating layer, which is located under a semiconductor layer, may be used so that the insulating layer may function as a layer for preventing leak of electric charges.
In the semiconductor memory device of the first aspect, an impurity concentration of the impurity region of the second transistor opposed to the cell plate may be higher than that of the other impurity region of the second transistor.
This structure can improve a capacity efficiency of an MOS capacity formed of the cell plate. The other impurity region described above is the impurity region spaced from the impurity region, which is opposed to the cell plate, with the channel region therebetween.
A semiconductor memory device according to a second aspect of the invention includes memory cells formed on a main surface of a semiconductor substrate and each having first and second transistors each having a gate electrode and impurity regions forming source/drain as well as one capacitor, and bit and word lines for controlling an operation of the memory cells. In this semiconductor memory device, a cell plate forming an electrode of the capacitor has a belt-like form extending along the word line, and the impurity regions of the first and second transistors are opposed to the cell plate, are continuous to each other and are located along the belt-like cell plate.
When arranging the memory cells in the array, connection is made in such a fashion that the impurity regions of the memory cells in each unit are opposed to the common cell plate. Therefore, when effecting exposure on the silicon substrate for forming the impurity regions of the memory cells, it is not necessary to space the individual impurity regions from each other, and the impurity regions can be continuous to each other. Therefore, the exposing margin can be remarkably large, and the yield can be significantly improved.
In the semiconductor memory device of the second aspect, the cell plate may be located as a layer at the same level as the gate electrode serving also as the word line.
According to this structure, the cell plate and the gate electrode can be formed of the same interconnection layer. Therefore, the memory cell including the memory cell capacitor can be formed substantially simultaneously with and thus in parallel with the cell array, and therefore, the manufacturing steps can be simplified.
A semiconductor memory device according to a third aspect of the invention includes a memory cell array formed of a plurality of memory cells arranged in rows and columns, and each provided with first and second transistors having gate electrodes and impurity regions forming sources/drains as well as one capacitor, bit lines corresponding to the plurality of columns and word lines corresponding to the plurality of rows; and a sense amplifier connected to the bit lines and used for amplifying a signal for normal access to the memory cells and refresh. In this semiconductor memory device, the first transistor is arranged as a transistor for normal access to be used for the normal access and not to be used for the refresh access. The second transistor is arranged as a transistor for refresh to be used for the refresh access and not to be used for the normal access.
According to the above structure, refreshing of the memory cell can be executed independently of the access for writing into and reading from the memory cell. Therefore, the efficiency of access to the semiconductor memory device can be improved, and the further the stability in holding signals stored in the memory cells can be improved. The xe2x80x9cnormal accessxe2x80x9d means the access for reading from and writing into the memory cell, and the xe2x80x9crefresh accessxe2x80x9d means the access for updating or renewing the capacitor signal.
In a semiconductor memory device of the third aspect, the bit lines may be formed of an access bit line and a refresh bit line, the first transistor may be connected to the access bit line, and the second transistor may be connected to the refresh bit line.
According to the above structure, voltages applied to the access bit line and the refresh bit line can be controlled for performing the access to the memory cell and the refresh independently of each other. Therefore, the access to the memory cell and the refresh thereof can be easily performed systematically within the semiconductor memory device.
The bit lines usually form pairs each including the bit line and the complementary bit line. Therefore, the access bit lines described above are formed of a pair of an access bit line and a complementary access bit line, and the refresh bit lines described above are formed of a refresh bit line and a complementary refresh bit line.
In the semiconductor memory device of the third aspect, the word lines may be formed of an access word line and a refresh word line, the sense amplifiers may include an access sense amplifier to be activated via the access word line and a refresh sense amplifier to be activated via the refresh word line, and the access sense amplifier and the refresh sense amplifier may operate independently of each other.
According to this structure, the access sense amplifier is activated by activating the access word line. Also, the refresh sense amplifier is activated by activating the refresh word line. As a result, the refresh word line is activated to activate the refresh sense amplifier independently of the access for read and write, and thereby the memory cell can be refreshed. Accordingly, the efficiency of access to the memory cell can be increased, and the stability in data holding by the memory cell can be improved.
The semiconductor memory device of the third aspect described above may employ a background refresh system for automatically refreshing the memory cell regardless of presence and absence of a refresh signal when the access sense amplifier is operating.
Owing to this structure, the refresh can be performed with a required frequency while accessing the memory cells with a sufficiently high access efficiency, and the data holding stability can be ensured.
A semiconductor memory device according to a fourth aspect of the invention includes a memory cell array formed of a plurality of memory cells arranged in rows and columns, and each provided with first and second transistors having gate electrodes and impurity regions forming sources/drains as well as one capacitor, bit lines corresponding to the plurality of columns and word lines corresponding to the plurality of rows; and a sense amplifier connected to the bit lines and used for amplifying a signal for access to the memory cells and refresh. In this semiconductor memory device, the memory cells are paired with complementary memory cells, respectively, and the sense amplifiers are formed of a normal sense amplifier connected to the bit line coupled to the memory cell and a complementary sense amplifier connected to a complementary bit line coupled to the complementary memory cell.
According to the above structure, the memory cell and the complementary memory cell can be considered as one unit of the memory cell pair. The memory cell pair includes two capacitors, which are complementary to each other so that H-data is written in one of the capacitors when L-data is written in the other. Owing to this relationship of the pair, the data pair formed of the H-data and L-data can be held more stably than the case where the H-data is solely written.
The two bit lines are connected to the normal sense amplifier, and the two complementary bit lines are connected to the complementary sense amplifier.
In the semiconductor memory device of the fourth aspect, the word lines may be formed of a first word line connected to the memory cell and a second word line connected to the complementary memory cell.
Owing to this structure, the normal sense amplifier row and the complementary sense amplifier row can be activated by using the first and second word lines, respectively. The access to and refresh of both the paired memory cells can be performed easily. Therefore, at least one of the sense amplifier and the complementary sense amplifier can be activated by activating at least one of the first and second word lines.
In the semiconductor memory device of the fourth aspect, one of the transistors in the memory cell is arranged as a transistor for normal access, and the other transistor is arranged as a transistor for refresh. Further, one of the transistors in the complementary memory cell is arranged as a transistor for normal access, and the other is arranged as a transistor for refresh.
Owing to this structure, the semiconductor memory device, which is of the complementary capacity type and can also retain the independence between the normal access and the refresh access, can be formed by using the memory cells of the two-transistor and one-capacitor type. Therefore, the stability against noises can be further improved, and the efficiency of access to a DRAM can be improved.
The semiconductor memory device of the fourth aspect may be configured such that the bit lines are formed of an access bit line and a refresh bit line, the word lines are formed of an access word line and a refresh word line, the sense amplifiers are formed of an access sense amplifier and a refresh sense amplifier, the normal access transistor in the memory cell is connected to the access bit line, the refresh transistor in the memory cell is connected to the refresh bit line, the normal access transistor in the complementary memory cell is connected to the complementary access bit line, and the refresh transistor in the complementary memory cell is connected to the complementary refresh bit line.
Owing to the above structure, the semiconductor memory device, which is of the complementary capacity type and also retains the independence between the normal access and the refresh access, can be produced inexpensively by using the memory cells of the two-transistor and one-capacitor type without significantly modifying a conventional manufacturing system.
The semiconductor memory device of the fourth aspect may include a switching control circuit for eliminating a complementary relationship between the memory cell and the complementary memory cell, establishing an equivalent relationship between the memory cell and the complementary memory cell, and operating both the memory cells equivalently.
According to this structure, the same semiconductor memory device can be used for arbitrarily selecting the circuit of the complementary capacity and the circuit of the normal and thus non-complementary capacity. As a result, the two circuits can be selected depending on the purpose of use and circumferential device environments, and depending on whether the complementary capacity type is to be selected for placing importance on the stability of data or the non-complementary capacity type is to be selected for placing importance on the memory density.
In the semiconductor memory device of the fourth aspect, the switching control circuit may include a sense amplifier connection control circuit for eliminating the complementary relationship by changing the state of connection of the sense amplifier only to the normal bit line to the state of connection to the normal and complementary bit lines, and changing the state of connection of the complementary sense amplifier only to the complementary bit line to the state of connection to the access bit line and the complementary access bit line different from the normal bit line and the complementary bit line.
According to this structure, either of the foregoing two arrangements can be selected merely by switching the foregoing connection switch without changing the arrangement in the semiconductor memory device.
A semiconductor memory device of a fifth aspect of the invention includes a memory array provided with memory cells arranged in rows and columns, and each including at least one transistor having a gate electrode and impurity regions forming source/drain as well as one capacitor, bit lines corresponding to the plurality of columns and word lines corresponding to the plurality of rows. The semiconductor memory device includes a cell plate forming one of electrodes of the capacitor and using the impurity region as an opposite electrode, and a cell plate potential changing circuit for changing the potential on the cell plate.
This structure can compensate for lowering of the potential due to, e.g., leak of the potentials of H-data from the capacitor, and can prevent vanishing or deterioration of the stored data. The potential changing circuit may be a cell plate line driver formed of pMOS and nMOS connected to a cell plate line.
In the semiconductor memory device of the fifth aspect, it is desired that the cell plate is arranged for each of the word lines.
The above structure can provide the semiconductor memory device, which can hold the stored signals with high stability, and can be inexpensive owing to reduction in cost of photomasks and others achieved by the simplified memory array.
According to the semiconductor memory device of the fifth aspect, it is desired that the cell plate has a belt-like form extending along the word line, and the memory array is positioned along the belt-like cell plate.
For example, the memory cells of the second aspect may be used as the memory cells arranged in accordance with this fifth aspect, in which case the semiconductor memory device of the fifth aspect and the cell plate potential changing circuit can have very simple structures. Therefore, it is possible to provide the semiconductor memory device, which has good storage stability and is very inexpensive.
According to the semiconductor memory device of the fifth aspect, it is desired that the cell plate potential changing circuit is a time-varying potential changing circuit for correcting the potential on the cell plate varying with time due to leak of potentials in the capacitor.
In this structure, when the potential changes oppositely to the change causing loss of the H-data, i.e., from a low level to a high level, compensation for the H-data can be performed by the coupling effect between the cell plate and the storage node (impurity region). As a result, it is possible to compensate efficiently for the charge-leak of H-data, which occurs during intervals between refresh operations.
According to the semiconductor memory device of the fifth aspect, the cell plate potential changing circuit can reset an amount of change effected on the cell plate when accessing the memory cell.
When the refresh access or normal access is effected on the memory cell, the cell plate is set to L-level. According to the above structure, compensation for the charge-leak of the capacitor can be performed in accordance with the cycles of the above.
According to the semiconductor memory device of the fifth aspect of the invention, the cell plate potential changing circuit may change the potential on the cell plate by flowing a current through the capacitor.
For compensating for the leak of charges in the capacitor, the current can be gradually supplied from a power supply side to the capacitor so as to raise the potential on the cell plate. As a result, deterioration of the data signal in the capacitor can be prevented.
In the semiconductor memory device of any one of the foregoing third to fifth aspects, it is desired that the memory cell is formed of the memory cell of the first or second aspect.
According to the above structure, the memory cell of the two-transistor and one-capacitor type can be formed in a small region through steps prepared only by making a simple change to conventional steps of manufacturing the semiconductor memory device. In the process of manufacturing an integrated circuit of the memory array, the memory cells can be arranged at a high density without making a significant change to the conventional steps of manufacturing the semiconductor memory device. As a result, the semiconductor memory device, which has good data holding stability, has a high-density structure and exhibits high yield, can be manufactured at a low cost.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.